1. Field of the Invention
The present invention relates to techniques for improving computer system performance. More specifically, the present invention relates to a method and an apparatus for enforcing memory reference ordering requirements, such as Total Store Ordering (TSO), at the L1 cache level.
2. Related Art
Advances in semiconductor fabrication technology have given rise to dramatic increases in microprocessor clock speeds. This increase in microprocessor clock speeds has not been matched by a corresponding increase in memory access speeds. Hence, the disparity between microprocessor clock speeds and memory access speeds continues to grow, and is beginning to create significant performance problems. Execution profiles for fast microprocessor systems show that a large fraction of execution time is spent not within the microprocessor core, but within memory structures outside of the microprocessor core. This means that the microprocessor systems spend a large fraction of time waiting for memory references to complete instead of performing computational operations.
Efficient caching schemes can help reduce the number of memory accesses that are performed. However, when a memory reference, such as a load operation generates a cache miss, the subsequent access to level-two (L2) cache or memory can require dozens or hundreds of clock cycles to complete, during which time the processor is typically idle, performing no useful work.
A number of forms of “speculative execution” have been proposed or are presently used to hide this cache-miss latency. Some processors support out-of-order execution, in which instructions are kept in an issue queue, and are issued “out-of-order” when operands become available. A given instruction is retired from the issue queue only when all preceding instructions have completed.
Some processor designers have proposed generating a checkpoint and entering a “scout mode” during processor stall conditions. In scout mode, instructions are speculatively executed to prefetch future loads and stores, but results are not committed to the architectural state of the processor. For example, see U.S. patent application Ser. No. 10/741,944, filed 19 Dec. 2003, entitled, “Generating Prefetches by Speculatively Executing Code through Hardware Scout Threading,” by inventors Shailender Chaudhry and Marc Tremblay. This solution to the latency problem eliminates the complexity of the issue queue. However, it suffers from the disadvantage of having to re-compute results of computational operations that were performed during scout mode.
To avoid performing these re-computations, processor designers have proposed entering an “execute-ahead” mode, wherein instructions that cannot be executed because of unresolved data dependencies are deferred, and wherein other non-deferred instructions are executed in program order. When an unresolved data dependency is ultimately resolved during execute-ahead mode, the system executes deferred instructions in a deferred mode, wherein deferred instructions that are able to be executed are executed in program order, and wherein other deferred instructions that still cannot be executed because of unresolved data dependencies are deferred again. For example, see U.S. patent application Ser. No. 10/686,061, filed 14 Oct. 2003, entitled, “Selectively Deferring the Execution of Instructions with Unresolved Data Dependencies as They Are Issued in Program Order,” by inventors Shailender Chaudhry and Marc Tremblay.
One problem with the above-described techniques for performing speculative execution is that it is hard to ensure that a multiprocessor adheres to a specific memory model, such as Total Store Ordering (TSO), as is required for correct operation of many parallel applications. For example, for a given thread, the TSO memory model requires that: (1) any two loads must complete in program order; (2) any two stores must complete in program order; (3) any store must complete after an earlier load in program order. However, note that loads can overtake subsequent stores if there is no Read-After-Write (RAW) hazard. Furthermore, as stores are visible to all threads, there must be a total ordering of all stores and a partial ordering of loads and stores.
To ensure that memory models (such as TSO) are not violated, some systems use a memory-disambiguation buffer to track loads that have completed during speculative execution. Store operations that take place during speculative execution are compared against entries in the memory-disambiguation buffer to determine whether the store can potentially cause a violation of the memory model. If so, the system can perform some type of remedial action. Unfortunately, memory-disambiguation buffers are generally implemented as large Content-Addressable Memory (CAM) structures, which do not scale well as systems support larger amounts of concurrent execution. For example, it is very hard to build a large CAM structure with a large number of ports to support concurrent accesses to a banked L2 cache.
Hence, what is needed is a method and an apparatus for enforcing memory models, such as TSO, without the drawbacks of existing mechanisms, such as memory-disambiguation buffers.